The area of each memory cell has been reduced to 0.16micron2 - a 50% size reduction from the previous generation. The on-chip peripheral CMOS circuitry has been optimised for the 1.8V power supply range used in mobile phones and other wireless applications.

A new surface channel transistor design features cobalt salicide and a



triple-metal interconnect scheme. Transistor driving currents have been more



than doubled compared with the devices used in the current 0.15micron



technology.



The process uses well-proven 248nm lithography and aluminum metal



interconnects. Ramp-up in Agrate will be followed by ST's fabs in Catania



and Singapore. All three fabs currently mass produce 0.15micron Flash



memories.



The first 0.13micron product is a 1.8V, 64Mbit device featuring a multiple



bank architecture and synchronous burst read mode. This is targeted at the



3G mobile phone market. This will be followed by 128Mbit and higher density



products.







SanDisk and Toshiba will jointly develop 90nm process technology aimed at



NAND Flash memory production. The work calls for various capacities



including 2Gbit and 4Gbit multi-level cell (MLC) NAND flash memory devices



as well as various smaller densities. The 90nm technology will allow for the



doubling of capacities from the previous 130nm generations. Both companies



plan to offer MLC NAND flash in addition to binary NAND flash using the same



process. SanDisk and Toshiba expect to sample 90nm devices in H2 2003 with



production scheduled for Q1 2004.



"We are already working on future-generation, leading-edge technology



including 70nm and 55nm process technology that will assure more powerful



NAND devices and cultivate new applications," reports Masashi Muromachi,



general manager of Toshiba's Memory division.



The 90nm NAND memory chips will be produced for both companies in Toshiba's



fab at Yokkaichi, Japan, under their FlashVision joint venture.